;********************************************************************** ; * ; Filename: PMB2306TNorteldual.ASM * ; Date: 13th March 2004 * ; File Version: 2.00 * ; * ; Author: John Worsnop G4BAO * ; Based on a 1998 program for the 16C84 by Hannes Illipe, SM6PGP * ; * ;This program loads the both LO PLLs, both PMB2306, in a * ;Nortel/Ionica RTB home unit (a "Nortel Pizza") with divider and * ;status data. This allows it to be used as 3400 to 50 MHz transverter* ;It produces a first LO of 2534.387895MHz to convert the 3400MHz * ;Amateur band to a 865.612105MHz 1st IF, and a second LO of * ;815.612105MHz for further conversion down to 50MHz * ; * ;GPIO-0 is COMMON DATA, GPIO-1 is COMMON CLOCK GPIO-2 is SHF ENABLE * ;GPIO-5 is UHF ENABLE * ;********************************************************************** ; * ; Files required: * ; PC12F629.inc - processor specific variable definitions * ; * ; * ;********************************************************************** ; * ; Notes: * ; Version 2 loads both the SHF and the UHF LO PMB2206T * ;********************************************************************** list p=PIC12F629 ; list directive to define processor #include ; processor specific variable definitions __CONFIG _MCLRE_OFF & _CP_OFF & _BODEN_ON & _PWRTE_ON & _WDT_ON & _INTRC_OSC_NOCLKOUT ;************************************************************ ; Register definitions ;************************************************************ CBLOCK 0x20 NO_O_B ;No of bits STAT1 ;data for pll status register STAT2 ;data for pll status register NA_CNT1 ;data for pll N/A counter NA_CNT2 ;data for pll N/A counter NA_CNT3 ;data for pll N/A counter R_CNT1 ;data for pll R counter R_CNT2 ;data for pll R counter R_CNT3 ;data for pll R counter count ;counter to check which synth we are loading Enable ENDC oscalval EQU 0x3FF ;************************************************************ ; GPIO port bit definitions ;************************************************************ ORG 0x000 ; processor reset vector movlw 03h movwf PCON ; re-set BOR and POR flags in PCON goto main ; go to beginning of program ORG 0x004 ; interrupt service routine goto $ ; No interrupts used ; ;********************************************************************************************* main ;configure the IO ports clrf GPIO bsf STATUS,RP0 ;*****************bank 1******************** movlw 08h ;Set up GP0,1,2 as outputs. GP0 is data, GP1 is clock GP2 is SHF enable, ;GP5 is UHF enable movwf TRISIO ;calibrate the internal 4MHz oscillator call oscalval ;Get the cal value movwf OSCCAL ;Calibrate ;Configure the watchdog timer movlw 08h movwf OPTION_REG ;ASSIGN PRESCALER (1:1) TO WDT using 08h in the w register ; set the counter to zero clrf count ;********************************************************************************************* ; Section 1 Load up the SHF synthesiser ;Rdiv=25, Ndiv=17, Adiv=6 PD=1mA, Dual mode, 1.3ns antibacklash, * ;PD neg ;********************************************************************************************* ;Load RAM registers with synth data for SHF section. LSB appears as first bit at GPIO ; Status 2 register movlw 0x3E ;first byte of status2 reg data. movwf STAT1 ;0011 0110 movlw 0xAA ;second byte of status2 reg data. movwf STAT2 ;1010 1010 ; N/A counter movlw 0x30 ;first byte of N/A counter data movwf NA_CNT1 ;0011 0000 movlw 0x00 ;second byte of N/A counter data movwf NA_CNT2 ;0000 0000 movlw 0x31 ;third byte of N/A counter data movwf NA_CNT3 ;0010 0001 ; R counter movlw 0x00 ;first byte of R counter data movwf R_CNT1 ;0000 0000 movlw 0x00 ;second byte of R counter data movwf R_CNT2 ;0000 0000 movlw 0xE6 ;third byte of R counter data movwf R_CNT3 ;1100 0110 ;************************************************************ ; enable I/O line definitions ;************************************************************ movlw 0x04 movwf Enable ; enable line for SHF synth is GPIO-2 ;************************************************************ loadsynth ;This code section loads the PLL status2 register bcf STATUS,RP0 ;*****************bank 0****************** movlw 08H ;set number of bits to be sent to 8 movwf NO_O_B firstbyteS movf STAT1,0 ;move contents of STAT1 to W reg andlw 0x01 ;MASK ALL EXCEPT DATA I/O LINE BIT iorlw 0x02 ;PUT CLK HIGH movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT andlw 0x01 ;PUT CLK LOW WITH DATA movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT rrf STAT1,1 ;ROTATE BYTE FOR NEXT DATA BIT decfsz NO_O_B,1 ;DECREMENT, CHECK THAT ALL BITS SENT goto firstbyteS ;loop back ; movlw 08H ;otherwise, reset number of bits to be sent to 8 movwf NO_O_B secondbyteS movf STAT2,0 ;move contents of STAT2 to W reg andlw 0x01 ;MASK ALL EXCEPT DATA I/O LINE BIT iorlw 0x02 ;PUT CLK HIGH movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT andlw 0x01 ;PUT CLK LOW WITH DATA movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT rrf STAT2,1 ;ROTATE BYTE FOR NEXT DATA decfsz NO_O_B,1 ;DECREMENT, CHECK THAT ALL CLEAR goto secondbyteS ;loop back ;ELSE CLEAR AND OUTPUT ENABLE ; movf Enable,0 ;load w with enable value movwf GPIO ;PUT ENABLE HIGH TO GPIO sleep ;WAIT FOR WDT TIMEOUT clrw ;CLEAR W REG movwf GPIO ;SEND NULL TO GPIO ;********************************************************************************************* ;This code section loads the N and A registers movlw 08H ;load NO_O_B with 08H movwf NO_O_B firstbyteNA movf NA_CNT1,0 ;MOVE NA_CNT1 TO W REG andlw 0x01 ;MASK ALL EXCEPT DATA I/O LINE BIT iorlw 0x02 ;PUT CLK HIGH movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT andlw 0x01 ;PUT CLK LOW WITH DATA movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT rrf NA_CNT1,1 ;ROTATE BYTE FOR NXT DATA decfsz NO_O_B,1 ;DECREMENT CHECK THAT ALL CLEAR goto firstbyteNA ;loop back movlw 08H ;load NO_O_B with 08H movwf NO_O_B secondbyteNA movf NA_CNT2,0 ;MOVE NA_CNT1 TO W REG andlw 0x01 ;MASK ALL EXCEPT DATA I/O LINE BIT iorlw 0x02 ;PUT CLK HIGH movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT andlw 0x01 ;PUT CLK LOW WITH DATA movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT rrf NA_CNT2,1 ;ROTATE BYTE FOR NXT DATA decfsz NO_O_B,1 ;DECREMENT CHECK THAT ALL CLEAR goto secondbyteNA ;loop back ; movlw 07H ;load NO_O_B with 07H movwf NO_O_B thirdbyteNA movf NA_CNT3,0 ;MOVE NA_CNT3 TO W REG andlw 0x01 ;MASK ALL EXCEPT DATA I/O LINE BIT iorlw 0x02 ;PUT CLK HIGH movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT andlw 0x01 ;PUT CLK LOW WITH DATA movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT rrf NA_CNT3,1 ;ROTATE BYTE FOR NXT DATA decfsz NO_O_B,1 ;DECREMENT CHECK THAT ALL CLEAR goto thirdbyteNA ;loop back ; movf Enable,0 ;load w with Enable value movwf GPIO ;PUT ENABLE HIGH TO GPIO sleep ;WAIT FOR WDT TIMEOUT clrw ;CLEAR W REG movwf GPIO ;SEND NULL TO GPIO ;********************************************************************************************* ;This code section loads the R register movlw 08H ;load NO_O_B with 08H movwf NO_O_B firstbyteR movf R_CNT1,0 ;MOVE R_CNT1 TO W REG andlw 0x01 ;MASK ALL EXCEPT DATA I/O LINE BIT iorlw 0x02 ;PUT CLK HIGH movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT andlw 0x01 ;PUT CLK LOW WITH DATA movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT rrf R_CNT1,1 ;ROTATE BYTE FOR NXT DATA decfsz NO_O_B,1 ;DECREMENT CHECK THAT ALL CLEAR goto firstbyteR ;loop back ;ELSE CLEAR WITH FIRST BYTE ; movlw 08H ;load NO_O_B with 08H movwf NO_O_B secondbyteR movf R_CNT2,0 ;MOVE R_CNT2 TO W REG andlw 0x01 ;MASK ALL EXCEPT DATA I/O LINE BIT iorlw 0x02 ;PUT CLK HIGH movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT andlw 0x01 ;PUT CLK LOW WITH DATA movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT rrf R_CNT2,1 ;ROTATE BYTE FOR NXT DATA decfsz NO_O_B,1 ;DECREMENT CHECK THAT ALL CLEAR goto secondbyteR ;loop back ;ELSE CLEAR TO PUT OUT ENABLE ; movlw 08H ;load NO_O_B with 08H movwf NO_O_B thirdbyteR movf R_CNT3,0 ;MOVE R_CNT3 TO W REG andlw 0x01 ;MASK ALL EXCEPT DATA I/O LINE BIT iorlw 0x02 ;PUT CLK HIGH movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT andlw 0x01 ;PUT CLK LOW WITH DATA movwf GPIO ;OUTPUT TO GPIO sleep ;WAIT FOR WDT TIMEOUT rrf R_CNT3,1 ;ROTATE BYTE FOR NXT DATA decfsz NO_O_B,1 ;DECREMENT CHECK THAT ALL CLEAR goto thirdbyteR ;loop back ;ELSE CLEAR TO PUT OUT ENABLE ; movf Enable,0 ;load w with enable value movwf GPIO ;PUT ENABLE HIGH TO GPIO sleep ;WAIT FOR WDT TIMEOUT clrw ;CLEAR W REG movwf GPIO ;SEND NULL TO GPIO incf count,1 btfsc count,1 ;if count >=2 (bit 1 of count is set=1) then we have finished, so go to sleep until reset goto ENDLOOP ;********************************************************************************************* ; Section 2 Load up the UHF synthesiser ;Rdiv=180, Ndiv=82, Adiv=31 PD=1mA, Dual mode, 1.3ns antibacklash, * ;PD pos ;********************************************************************************************* ;Load RAM registers with synth data for UHF section. LSB appears as first bit at GPIO ; Status 2 register movlw 0x3E ;first byte of status2 reg data. movwf STAT1 ;0011 1110 movlw 0xAA ;second byte of status2 reg data. movwf STAT2 ;1010 1010 ; N/A counter movlw 0x48 ;first byte of N/A counter data movwf NA_CNT1 ;0111 1100 movlw 0x40 ;second byte of N/A counter data movwf NA_CNT2 ;0100 0000 movlw 0x37 ;third byte of N/A counter data movwf NA_CNT3 ;0010 1001 ; R counter movlw 0x00 ;first byte of R counter data movwf R_CNT1 ;0000 0000 movlw 0x40 ;second byte of R counter data movwf R_CNT2 ;0000 0000 movlw 0xCB ;third byte of R counter data movwf R_CNT3 ;1100 0110 ; enable I/O line definitions movlw 0x20 movwf Enable ; enable line for UHF synth is GPIO-5 goto loadsynth ENDLOOP sleep ;WAIT FOR WDT TIMEOUT sleep sleep sleep sleep sleep sleep sleep sleep goto ENDLOOP ;START NEW CYCLE END ; directive 'end of program'